By Topic

VLSI Chip Interconnection Technology Using Stacked Solder Bumps

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
N. Matsui ; Applied Electronics Lab.,Japan ; S. Sasaki ; T. Ohsaki

A new type of flip-chip interconnection technology using stacked solder bumps supposed by polyimide films has been developed to improve the reliability of large-size VLSI chip interconnections. This technology is based on the principle that the higher the equivalent bump height; the smaller will be the shear strain. Numerical analysis shows that the increased number Of solder bump stacks reduces the shear strain in solder joints. In particular, thermal shock test results indicate that the lifetime of the double-stacked solder bumps joining 20 x 20-mm silicon chips to alumina ceramic boards is 60 times that of conventional . . unstacked bumps.

Published in:

IEEE Transactions on Components, Hybrids, and Manufacturing Technology  (Volume:10 ,  Issue: 4 )