Multichip Packaging Design for VLSI-Based Systems

The introduction of many VLSI devices into system designs is placing new requirements on the packaging technologies that are used to interconnect devices and assemble systems. These requirements include the assembly of high pin out (up to 500 I/O's) devices, the ability to sustain synchronous system operation at frequencies up to 100 MHz, and cooling at thermal loads greater than 1 W/cm
²
. A new packaging technology is described that will overcome many of the limitations of conventional packaging. The new technology has the capability for assembling devices with more than 200 I/O's, a maximum signal lead length less than 20 cm, a power and ground lead inductance less than 0.1 nH, a signal lead capacitance less than 20 pF, and a cooling capability greater than 1 W/cm
²
. The substrate for the proposed new packaging technology is a silicon wafer. The power and ground are distributed by means of copper planes on either side of the substrate. Two signal layers are positioned above the power plane using a polyimide dielectric material. The signal leads are a minimum of 10 µm wide. With 10-µm-thick polymer, the line capacitance is ~ 1 pF/cm. Copper metallization is · used to achieve a resistance of 10
\Omega
/cm for the minimum width signal leads with 2-µm-thick conductors. Devices are attached to the interconnection substrate by means of solder. The solder technology was chosen because it is repairable, provides a low-inductance (< 1 nH) connection between chip and substrate, and enables I/O pads to be positioned over the area of the chip. The matched thermal expansion coefficient between the substrate and chip results in a mechanically stable solder attachment. This new packaging technology has been demonstrated by means of a prototype vehicle. Three chips from the WE
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32100 chip set: CPU, memory management unit (MMU), and math accelerator unit (MAU), have been flip-chip bonded and interconnected together on a 1.3 x 3.0-cm substrate. The chips have been spaced 500 µm apart. The assembly has been bonded to a metal heat sink using a compliant adhesive layer to minimize stresses in the silicon substrate. The chip-to-heat sink thermal resistance for the assembly is 5°C/W (junction to case). A 160 I/O multilayer printed wiring board package has been used to fan out from the edge of the substrate to pins on a 100-mil grid. Wire bonds electrically connect the substrate to the package and provide for chip backside grounding. A protective cover completes the package assembly. In summary, significant improvements in system performance can be achieved with the new multichip technology. Compared to conventional packaging, a factor of 3 improvement in system operating frequency is expected when IC's are designed specifically for the technology. Additionally, system size and power dissipation can be reduced by a factor of seven and 30 percent, respectively.