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A microprocessor design for multilevel security

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2 Author(s)
D. B. Clifton ; Harris Semicond., Melbourne, FL, USA ; E. B. Fernandez

A protection architecture, specifically designed to meet the requirements for secure hardware is described. This architecture, which is called the KEVEC-32 (Kernelized Verifiable CISC processor), enforces a multilevel, categorized model of security. Intended for multilevel applications, the microprocessor uses several unique features to provide a high degree of security. The most significant of these is a separation of processor privilege states and data classification. The processor also provides enhanced access control through a domain-based virtual addressing system. An extended 56-bit virtual address provides accountability by assigning each user with a specific address space. Finally, security validation is facilitated by organizing all security-related portions of hardware into a secure kernel

Published in:

Aerospace Computer Security Applications Conference, 1988., Fourth

Date of Conference:

12-16 Dec 1988