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Sampled data analog signal processor

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2 Author(s)
K. Jundi ; Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA ; R. Siferd

A CMOS integrated circuit implementation of a sampled data analog signal processor which incorporates four-quadrant analog multipliers as a key component is presented. The four-quadrant multiplier facilitates signed analog inputs for both data and transfer function coefficients and thereby provides the same flexibility as digital processors for programmable and adaptive applications. Unique architectural features include a parallel configuration for the sample-and-hold circuit and a capacitor summing circuit. The processor was fabricated in a 2-micron double-poly, double-metal process

Published in:

Aerospace and Electronics Conference, 1990. NAECON 1990., Proceedings of the IEEE 1990 National

Date of Conference:

21-25 May 1990