Gate speed improvement at minimal power dissipation

We introduce a new gate sizing rule for significantly improving the speed performance of static logic paths designed in submicron CMOS technology. This methodology is based on the definition of local gate sizing criterion. It is directly deduced from analytical models of the output transition time and of the short circuit power dissipation, which are validated on a 0.18 μm CMOS process. This sizing methodology is shown to offer a low power implementation alternative that can be used as an initial solution, prior to any logic path optimization.