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Experimental checking of fault susceptibility in a parallel algorithm

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2 Author(s)
Derezinska, A. ; Inst. of Comput. Sci., Warsaw Univ. of Technol., Poland ; Sosnowski, J.

We deal with the problem of analyzing fault susceptibility of a parallel algorithm designed for a multiprocessor array (MIMD structure). This algorithm realizes quite a complex communication protocol in the system. We present an original methodology of the analysis based on the use of a software implemented fault injector. The considered algorithm is modeled as a multithreaded application. The experiment set up and results are presented and commented. The performed experiments proved relatively high natural robustness of the analyzed algorithm and showed further possibilities of its improvement.

Published in:

Parallel Computing in Electrical Engineering, 2002. PARELEC '02. Proceedings. International Conference on

Date of Conference:

2002