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Architecture-to-task optimization system (ATOS) for parallel multi-mode data-flow architectures on a base of a partially reconfigurable computing platform

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3 Author(s)
F. Chayab ; Dept. of Electr. & Comput. Eng., Ryerson Polytech. Univ., Toronto, Ont., Canada ; L. Kirischian ; L. Szajek

This paper presents an approach of automated architecture synthesis for a wide class of parallel multi-mode data-flow embedded computing systems. This approach is based on the method of automated synthesis of multi-mode architectures. This method allows finding the best correspondence between a multi-mode data-flow application (task) and its parallel processing architecture. This method has been implemented in an architecture-to-task optimization system (ATOS) based on a partially reconfigurable computing platform (PRCP). It was estimated that ATOS could synthesize a complete architecture for an application presented in the form of a data-flow graph within a few seconds including emulation and performance measurements on the PRCP. The proposed approach can dramatically decrease the cost of the R&D design stage and time-to-market for a wide range of parallel multi-mode embedded computing systems.

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Parallel Computing in Electrical Engineering, 2002. PARELEC '02. Proceedings. International Conference on

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