By Topic

A 1.2 GHz high-speed 256-bit shift register LSI

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Mori, H. ; OKI Electr. Ind. Co. Ltd., Tokyo, Japan ; Tsukuda, A. ; Nishimura, H. ; Takada, M.
more authors

The authors have developed a high-speed 256-bit shift register LSI intended for use in gigabit-rate signal storage applications in GaAs MESFET DCFL/SBFL (direct-coupled FET logic/superbuffer FET logic) circuits. This shift register has serial data input and serial data output composition, suitable for line memory usage. To attain both high-speed and low power characteristics, the authors used a serial-input-data to parallel-internal-data and parallel-internal-data to serial-output-data conversion system. The maximum clock rate under which this device can operate is 1.2 GHz. It has a low (1.2-W) power consumption from a single 2-V power supply.<>

Published in:

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1988. Technical Digest 1988., 10th Annual IEEE

Date of Conference:

6-9 Nov. 1988