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CMOS scaling to 25 nm gate lengths

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2 Author(s)
S. Kubicek ; IMEC, Leuven, Belgium ; K. De Meyer

In this paper some of the device and process issues of scaling CMOS technology down to 25 nm gate lengths are reviewed. First scaling is discussed front a device perspective and the main device related issues are identified. An overview of the historical trends and predictions by the ITRS roadmap follows. Implications of the scaling predictions for the specific device process modules are reviewed and recent experimental data are presented.

Published in:

Advanced Semiconductor Devices and Microsystems, 2002. The Fourth International Conference on

Date of Conference:

14-16 Oct. 2002