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A maximum pipelined CORDIC architecture for inverse kinematic position computation

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2 Author(s)
Lee, C.S. ; Purdue University, West Lafayette, IN, USA ; Chang, P.

A cost-effective coordinate rotation digital computer (CORDIC) architecture is described for the computation of inverse kinematic position solution based on a functional decomposition of the closed-form joint equations. The functional decomposition shows a limited amount of parallelism with a large amount of sequentialism in the flow of computation and data dependencies and reveals the requirement for computing a large set of elementary operations: multiplications, additions, divisions, square roots, trigonometric functions and their inverse. However, these elementary operations, in general, cannot be efficiently computed in general-purpose uniprocessor computers. The CORDIC algorithms are the natural candidates for efficiently computing these elementary operations and the interconnection of these CORDIC processors to exploit the great potential of pipelining provides a better solution for computing the inverse kinematic position solution. The functional decomposition of the inverse kinematic position solution into a set of computational tasks can be represented as a directed task graph. The inclusion of input data modifies the task graph to an acyclic data dependency graph (ADDG). The nodes of the ADDG correspond to the computational modules, each of which can be realized by a CORDIC processor. The operands or data move along the edges, each of which connects a pair of nodes. Due to different paths and computation time for each CORDIC processor, operands may arrive at multi-input modules at different arrival time, causing a longer pipelined time. Delay buffers may be inserted at various paths to achieve a balanced ADDG. The optimal buffer assignment problem is reduced to an integer linear optimization problem which can be solved easily by computers. The realization of the balanced ADDG results in a maximum pipelined CORDIC architecture with a minimum number of delay buffer stages for the computation of inverse kinematic position solution.

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Robotics and Automation, IEEE Journal of  (Volume:3 ,  Issue: 5 )