Design methodology of a 1.2-/spl mu/m double-level-metal CMOS technology

An advanced high-performance CMOS process and associated gate array and semicustom design approaches are described. Designed for rapid custom application, the process utilizes an n-well 1.2-/spl mu/m gate length and two layers of metal. The gate array has a density of 10000 2-input gates with typical delays of 1.25 ns, while the semicustom approach offers densities of 30000 gates with typical loaded delays of 1.0 ns.