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A precision FET-less sample-and-hold with high charge-to-droop current ratio

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2 Author(s)

A monolithic sample-and-hold amplifier designed without field-effect transistors is described. Various sample-and-hold configurations are compared and their merits are discussed. Unique features of the design include a diode-bridge switch and a current booster with 50 mA of drive capability to charge the hold capacitor during large signal acquisition. The output amplifier's operating conditions are changed under logic control; it functions as a fast follower in the sample mode, and as a low input current amplifier in the hold mode. Performance characteristics include: 3.5-/spl mu/s acquisition time to 0.1 percent with a 5000-pF hold capacitor, 50 pA of droop current from 0 to 70/spl deg/C, 10/SUP 9/ charge-to-droop current ratio, and 0.3 mV of zero-scale error.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:13 ,  Issue: 6 )

Date of Publication:

Dec. 1978

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