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A low-voltage IC timer

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2 Author(s)

The design of a low-voltage micropower timer is described. It is well known that if standard analog integrated n-p-n transistors are connected in a simple diode-biased current sink arrangement, the saturation of one of the transistors in the string drastically reduces the collector currents in the other transistors. By using this effect to indicate the onset of saturation, the timing capacitor's end-of-discharge voltage is sensed at one V/SUB cc(sat)/ above ground. When used as a low-duty cycle timer, or as a monostable, the circuit can achieve accuracies comparable to that of the industry standard 555 timer and can operate at supply voltages as low as 1 V.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:13 ,  Issue: 6 )