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High-speed bipolar logic circuits with low power consumption for LSI-a comparison

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2 Author(s)

Various high-speed bipolar logic circuits (CML, FECL, NTL, TTL, STL) are investigated and compared which exhibit gate delays far below 1 ns, even at a very low power dissipation per gate (e.g. 0.1 mW). Therefore, these circuits are best suited for LSI. It is shown that, by tailoring the circuit components (transistors, Schottky diodes) to the power dissipation P, the expected increase of the gate delay t/SUB D/ according to t/SUB D/~1/P can be shifted to surprisingly low values of P. Further, the simulations show that the Schottky clamp technique has considerable advantages concerning the switching speed at very low power dissipations, compared with the current-mode logic known to be fast. The results are explained by simple calculations.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:17 ,  Issue: 4 )

Date of Publication:

Aug 1982

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