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An analog CCD reformatting memory has been designed and fabricated using an n-channel double level polysilicon gate process. This unique CCD structure employs two-dimensional charge transfer cells in a 32/spl times/32 element array which is accessed by means of integrated CCD demultiplexer and multiplexer structures resulting in greater dynamic range than observed in previous line-addressed designs. The design and operation of this structure are discussed, and examples of applications in analog signal processor architectures are described.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:14
,
Issue:
6
)
Date of Publication: Dec. 1979
- Page(s):
- 1041 - 1048
- ISSN :
- 0018-9200
- Digital Object Identifier :
- 10.1109/JSSC.1979.1051313
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 January 2003
- Issue Date :
- Dec. 1979
- Sponsored by :
- IEEE Solid-State Circuits Society
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