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An analog CCD reformatting memory has been designed and fabricated using an n-channel double level polysilicon gate process. This unique CCD structure employs two-dimensional charge transfer cells in a 32/spl times/32 element array which is accessed by means of integrated CCD demultiplexer and multiplexer structures resulting in greater dynamic range than observed in previous line-addressed designs. The design and operation of this structure are discussed, and examples of applications in analog signal processor architectures are described.
Date of Publication: Dec. 1979