Referenced Items are not available for this document.
Presents a multichannel approach to the codec and filter subsystem found at the heart of digital PCM systems. The subsystem consists of a multichannel codec and associated transmit and receive filters, structured to produce a five-chip group handling eight subscriber channels. A 2.048 MHz master clock and a time slot zero (TSO) synchronization pulse are the only external drive requirements other than power supplies. Within the group, timing is generated internally and allows four groups to be cascaded to produce a 32-channel system with only 20 chips. With a target power consumption of only 62.5 mW/channel, the 8-channel group structure offers significant advantages in total power and board area, compared with the single-channel approach.
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:14
,
Issue:
6
)
Date of Publication: Dec. 1979
- Page(s):
- 953 - 960
- ISSN :
- 0018-9200
- Digital Object Identifier :
- 10.1109/JSSC.1979.1051303
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 January 2003
- Issue Date :
- Dec. 1979
- Sponsored by :
- IEEE Solid-State Circuits Society
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