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The design and characterization of a real-time correlator/electrically programmable transversal filter is presented, based on a novel functional multiplying structure in a standard single-level MOS LSI process. The analog information is sampled and held at fixed sites on the chip and the tap weights slide past them; the taps are digitized into 7 bits which control the selection of seven binary area-ratioed MOS capacitors per tap position. The rotation of the tap weights can reduce the effect of tap-weight errors but contributes to fixed pattern noise. Experiments using cascaded chips to build longer filters show excellent transfer-function agreement with theory. Dynamic range of the device is limited primarily by fixed pattern noise. This problem has been modeled and at present about a 45-dB dynamic range has been obtained for the heaviest doped chips when driven by input-signal amplitudes which allow better than 1-percent harmonic distortion. With improvements suggested, significant increases are expected in the dynamic range of the device.