By Topic

Techniques for reducing the peak power of a switching transistor with p-i-n diode load

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)

Describes techniques for reducing the peak power of switching transistor that reverse biases a p-i-n diode load. Particular emphasis is placed on a parallel combination of a Zener diode and an inductor and it is shown that, for an experimental p-i-n driver, the peak power is reduced from 252 to 90 W.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:12 ,  Issue: 5 )