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VMOS memory technology

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6 Author(s)

VMOS technology is discussed as it applies to semiconductor memory. A 45-ns 1-kbit static RAM with a die size of 81 mil×125 mil and a cell area of 3.0 square mils is presented. The device is fabricated with the original grounded-source version of the VMOS process. Design considerations and electrical data are given for a 30-ns scaled version of the RAM with a 55 mil×80 mil die size and a 1.25-square-mil cell area. Two new VMOS process options are presented. In one option the grounded-source limitation of VMOS is removed by the addition of diffused buried layers. These buried layers can be used as dynamic RAM storage capacitors. Electrical data are presented for a VMOS dynamic RAM cell whose area is 0.36 square mils (6-μm rules). In the third VMOS process option, an extra layer of polysilicon is added to the grounded-source process to fabricate an erasable programmable read only memory (EPROM) cell, also with a 0.36-square-mil area.

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Solid-State Circuits, IEEE Journal of  (Volume:12 ,  Issue: 5 )