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Network processors are emerging as a programmable alternative to the traditional ASIC-based solutions in scaling up the data-plane processing of network services. This work, rather than proposing new algorithms, illustrates the process of and examines the performance issues in, prototyping a DiffServ edge router with IXP1200. The external benchmarks reveal that though the system can scale to wire-speed of 1.8 Gbps in simple IP forwarding, the throughput declines to 180 Mbps∼290 Mbps when DiffServ is performed due to the double bottlenecks of SRAM and microengines. Through internal benchmarks, the performance bottleneck was found to be able to shift from one place to another given different network services and algorithms. Most of the result reported here remain the same for other NPs since they have similar architectures and components.