Pipelined parallel bidirectional shift (PPB) architecture for high speed serial access

Recently, dual-port RAMs[1][2] with serial rate ranging from 33MHz to 70MHz have been introduced for graphic system applications. However, higher resolution graphic displays, such as 770K pixels/ screen, require over 100MHz data rate. This paper describes a newly proposed technique named Pipelined Parallel Bidirectional shifts (PPB) Architecture. which provides high speed serial rate (100MHz) for high density dual-port memories.