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PLX: a fully subword-parallel instruction set architecture for fast scalable multimedia processing

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2 Author(s)
Lee, R.B. ; Archit. Lab. for Multimedia & Security, Princeton Univ., NJ, USA ; Fiskiran, A.M.

PLX is a small, fully subword-parallel instruction set architecture (ISA) designed for very fast multimedia processing, especially in constrained environments requiring low cost and power, such as handheld multimedia information appliances. In PLX, we select the most useful multimedia instructions added previously to microprocessors. We also introduce a few novel features: a new definition of predication requiring very few bits in each predicated instruction, and datapath scalability from 32-bit to 128-bit words, which allows different degrees of subword parallelism without any changes to the ISA. Performance results from basic multimedia kernels testify to PLX's superiority for multimedia processing.

Published in:

Multimedia and Expo, 2002. ICME '02. Proceedings. 2002 IEEE International Conference on  (Volume:2 )

Date of Conference:

2002