By Topic

Power and performance exploration of embedded systems executing multimedia kernels

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
Dasygenis, M. ; Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece ; Kroupis, N. ; Tatas, K. ; Argyriou, A.
more authors

The memory subsystem in modem embedded programmable architectures executing multimedia applications consumes a significant amount of energy. The designer has to take this fact into consideration, together with the system performance, in order to design devices portable or otherwise. An exploration approach for optimising the power and performance of the data-memory hierarchy as well as the instruction memory in the early system-design phase, is introduced. A power- and performance-efficient data-memory hierarchy is obtained by applying data-reuse transformations in a high-level description of the application, whereas the instruction-memory power optimisation, of the selected optimal data hierarchies of the previous step, is achieved by using a suitably selected cache memory. Furthermore, two cache energy models, namely the high-level power model and the architecture-dependent power model, are introduced. The experimental results, obtained with four well known motion-estimation kernels, provide an insight on the trade-offs among algorithm performance and energy consumption, comparing memory hierarchies with and without an instruction cache for the ARM programmable core. Comparisons results are also provided for choosing an optimal cache memory size

Published in:

Computers and Digital Techniques, IEE Proceedings -  (Volume:149 ,  Issue: 4 )