By Topic

On the jitter requirements of the sampling clock for analog-to-digital converters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Da Dalt, N. ; Mixed Signal Dept., Infineon Technol. AG, Villach, Austria ; Harteneck, M. ; Sandner, C. ; Wiesbauer, A.

In this work, the effect of sampling clock jitter on the SNR of an analog-to-digital (AD) conversion is investigated from a practical perspective. Aperture jitter analyses have been dealing up to now with white spectrum jitter. This assumption does not hold for the output of phase-locked loops (PLL)-like frequency synthesizers, where the spectrum is shaped by the loop transfer function. Based on a linear approximation, a powerful expression for the SNR is derived, applicable to a jitter process with a generic autocorrelation function and generic input signal. A lot of different definitions of jitter are available in the literature; this work addresses also the problem of identifying correctly among them the "effective" jitter for a given SNR. This can be profitably used in the specification as well as verification of the jitter requirements of a frequency synthesizer used as sampling clock generator in the AD converter systems. The results have been checked through numerical simulation.

Published in:

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on  (Volume:49 ,  Issue: 9 )