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The Counterflow Pipeline Processor (CFPP) Architecture is a RISC-based pipeline processor. It was proposed in 1994 as an asynchronous processor architecture. Recently, researches have implemented it as a synchronous processor architecture and later improved its design in terms of speed and performance by reducing average execution latency of instructions and minimizing pipeline stalling. In this paper, we survey the architecture and the key design issues such as implementation as a synchronous and an asynchronous architecture and discuss the advantages and disadvantages of these implementations. Further, our research on evaluating the performance of the counterflow pipeline processor architecture in relation to that of the traditional MIPS processor architecture is discussed.