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A differential-capacitance read scheme for FeRAMs

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5 Author(s)
Eslami, Y. ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada ; Sheikholeslami, A. ; Masui, S. ; Endo, T.
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A differential-capacitance read scheme keeps the plateline voltage constant at ground and begins sensing the stored data immediately after a wordline is raised, hence eliminating the time spent in conventional read schemes in raising the highly capacitive plateline and in charge sharing of the bitlines with the ferroelectric capacitors. The proposed read scheme is used in a 256/spl times/128-bit testchip that features both 2T-2C and 1T-1C cells in 0.35/spl mu/m technology. The read scheme achieves a 40% reduction in access time.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002

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