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The proposed pattern-matching engine achieves distance-measure adaptability through pattern encoding and can therefore cover a wide range of high-performance real-time applications. Key to short nearest-match times is a compact fully-parallel associative-memory core. The performance of a 9.75 mm/sup 2/ test-circuit in 0.6 /spl mu/m CMOS technology is about equivalent to a 32 bit computer with ITOPS. The test-circuit suggests possible pattern length /spl ges/768 equivalent bit, >10/sup 7/ pattern/sec throughput, <1.13% winner-input-distance error and <1.35 mW power dissipation per reference pattern.