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Crosstalk delay analysis of a 0.13-/spl mu/m-node test chip and precise gate-level simulation technology

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7 Author(s)

The impact of crosstalk on the delay was examined by measuring a test chip manufactured with a 0.13-/spl mu/m-node technology. This examination revealed three requirements for precise and fast gate-level simulation technology: (1) consideration of degradation change dependent on relative-signal-arrival-time over a wide range, (2) static timing analysis (STA) based operation, and (3) quantitative estimation of the degradation accumulation caused by multiple aggressors. A candidate for such simulation technology is provided. and its highly precise characteristic is demonstrated through measurements and simulations. In a test structure with a two-aggressor crosstalk, the maximum error between the measured and simulated degradations was reduced to less than one sixth of that with a conventional method.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002