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High performance devices available in a logic-based embedded DRAM process can be used to significantly improve eDRAM performance. However, random access cycle time of conventional eDRAMs remains around 6 ns. In this work, a novel destructive-read architecture that reduces the random access cycle time of an eDRAM by delaying the data write back operation to a later cycle is demonstrated. A single-ended direct sensing is employed to further speed up the random access cycle time of the eDRAM to 2.9ns.
Date of Conference: 13-15 June 2002