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A quadrature direct digital frequency synthesizer (DDFS) is fabricated in 0.35 μm CMOS using a new phase-to-sine conversion algorithm. It achieves a spurious-free dynamic range (SFDR) of 96 dB with small-sized lookup tables and appropriate arithmetic hardware. The prototype DDFS IC generates 16 b cosine and sine outputs with an output frequency tuning resolution of 0.03 Hz. It works at 150 MHz sampling rate, consuming 670 mW.
Date of Conference: 2002