Referenced Items are not available for this document.
A quadrature direct digital frequency synthesizer (DDFS) is fabricated in 0.35 μm CMOS using a new phase-to-sine conversion algorithm. It achieves a spurious-free dynamic range (SFDR) of 96 dB with small-sized lookup tables and appropriate arithmetic hardware. The prototype DDFS IC generates 16 b cosine and sine outputs with an output frequency tuning resolution of 0.03 Hz. It works at 150 MHz sampling rate, consuming 670 mW.
Published in:
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Date of Conference: 2002
- Page(s):
- 146 - 147
- Print ISBN:
- 0-7803-7310-3
- INSPEC Accession Number:
- 7432206
- Digital Object Identifier :
- 10.1109/VLSIC.2002.1015069
- Product Type:
- Conference Publications
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