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A 1.2 Gbps CMOS DFE receiver with the extended sampling time window for application to the SSTL channel

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4 Author(s)
Young-Soo Sohn ; Dept. of Electr. Eng., Pohang Inst. of Sci. & Technol., South Korea ; Seung-Joon Bae ; Hong-June Park ; Soo-In Cho

A CMOS DFE (decision feedback equalization) receiver with a negligible overhead in chip area and power consumption was implemented by cross-coupling the outputs of a conventional 2-way interleaving receiver to the other side of the input. Application of this receiver to the SSTL interface channel showed the increase of sampling time window by 60 /spl sim/120% at data rates from 800 Mbps up to 1.2 Gbps. Chip area and power consumption are 80/spl times/100 /spl mu/m and 2.5 mW respectively with a 0.25 /spl mu/m 1-poly 5-metal CMOS process at the supply voltage of 2.5 V.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002