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A 5 Gbps CMOS frequency tolerant multi phase clock recovery circuit

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5 Author(s)
T. Iwata ; Adv. LSI Technol. Dev. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan ; T. Hirata ; H. Sugimoto ; H. Kimura
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A clock and data recovery (CDR) circuit using multi phase gated VCO (MGVCO) technique for multi-channel high-speed serial interface was developed. This architecture can realize quick data acquisition and plesiochronous clocking capability. A 5 Gbps 32-channel test chip, designed in 0.18 /spl mu/m CMOS technology, achieved BER of <10/sup -12/ in 5 Gbps CDR operation with /spl plusmn/3% frequency tolerance for random incoming data of 2/sup 7/-1.

Published in:

VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference:

13-15 June 2002