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Four-way processor 800 MT/s front side bus with ground referenced voltage source I/O

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2 Author(s)
Thomas, T.P. ; Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA ; Young, I.A.

A 40 cm multi-drop bus shared by 5 test chips to emulate 4 processors and a chipset runs error free at 800 MT/s with 130 mV margin using Ground Referenced Voltage Source (GRVS) I/O scheme. For comparison, when the same test chip is programmed to use Gunning Transceiver Logic (GTL), the bus speed is 500 MT/s for the same 130 mV margin under identical conditions.

Published in:
VLSI Circuits Digest of Technical Papers, 2002. Symposium on

Date of Conference: 13-15 June 2002

Page(s):
70 - 71
Print ISBN:
0-7803-7310-3
INSPEC Accession Number:
7425693
Conference Location :
Honolulu, HI, USA
Digital Object Identifier :
10.1109/VLSIC.2002.1015048

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