Referenced Items are not available for this document.
This paper describes a 32 KB dual-ported L0 cache for 4.5 GHz operation in 1.2 V, 130 nm CMOS. The local bitline uses a Self Reverse Bias scheme to achieve -220 mV access transistor underdrive without external bias voltage or gate-oxide overstress. 11% faster read delay and 104% higher DC robustness (including 7x measured active leakage reduction) is achieved over optimized high-performance dual-Vt scheme.
Published in:
VLSI Circuits Digest of Technical Papers, 2002. Symposium on
Date of Conference: 13-15 June 2002
- Page(s):
- 48 - 49
- Print ISBN:
- 0-7803-7310-3
- INSPEC Accession Number:
- 7432189
- Conference Location :
- Honolulu, HI, USA
- Digital Object Identifier :
- 10.1109/VLSIC.2002.1015041
- Product Type:
- Conference Publications
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