Skip to Main Content
This paper describes a 32 KB dual-ported L0 cache for 4.5 GHz operation in 1.2 V, 130 nm CMOS. The local bitline uses a Self Reverse Bias scheme to achieve -220 mV access transistor underdrive without external bias voltage or gate-oxide overstress. 11% faster read delay and 104% higher DC robustness (including 7x measured active leakage reduction) is achieved over optimized high-performance dual-Vt scheme.
Date of Conference: 13-15 June 2002