By Topic

A test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
T. Hosokawa ; Design Technol. Dev. Dept., Semicond. Technol. Acad. Res. Center, Yokohama, Japan ; H. Date ; M. Muraoka

This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.

Published in:

VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE

Date of Conference:

2002