Referenced Items are not available for this document.
A simple solution for linearization of the MOS sampling switch is proposed. It improves the SFDR of a T/H circuit and is suitable for high-speed applications. Sampling at a constant gate-source voltage minimizes sampling errors due to variable MOS sampling switch ON-conductance and channel charge injection, and also eliminates input-dependent sampling instant variation. The proposed linearized T/H circuit is fabricated in a 0.35-μm CMOS process. Test measurements show the sampling of a 1 GHz signal.
Published in:
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
(Volume:5
)
Date of Conference: 2002
- Page(s):
- V-577 - V-580 vol.5
- Print ISBN:
- 0-7803-7448-7
- INSPEC Accession Number:
- 7454553
- Digital Object Identifier :
- 10.1109/ISCAS.2002.1010769
- Product Type:
- Conference Publications
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