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Class AB-D-G line driver for central office asymmetric digital subscriber line systems

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3 Author(s)
Shorb, J. ; Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA ; Allstot, D.J. ; Roze, R.

This paper describes the design of a line driver that can be used for the downstream central office ADSL (asymmetric digital subscriber line) channel. The design uses a 0.35 μm/3.3 V CMOS process, and has a hybrid architecture that combines a class-AB stage in parallel with two class-D stages, each with different supply voltages. Due to the low power supply voltage, an alternative class-AB stage is used, that achieves a higher output voltage swing than the traditional class-AB stage. Simulations to estimate the power consumption of this design resulted in 1.3 W for the central office downstream channel; 83% of the power is dissipated in the switching transistors, and the buffers that drive them. The architecture is flexible to additional circuit enhancements.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

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