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A 3.4-mW 128-MHz analog correlator for DS-CDMA wireless applications

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4 Author(s)
M. A. R. Eltokhy ; Dept. of Electron. & Inf. Syst., Osaka Univ., Japan ; B. -K. Tan ; T. Matsuoka ; K. Taniguchi

A new analog correlator circuit for a direct sequence code division multiple access (DS-CDMA) demodulator is proposed. The circuit consists of only 13 switches, 4 capacitors and 2 level shifters. Simulation with a code length of 127 reveals that the proposed circuit dissipates 3.4 mW at 128 MHz. The proposed circuit had been implemented into a Si chip using a 0.6 μm CMOS process. The occupation area of 256 μm×245 μm is estimated to be 9 times smaller compared to other reported equivalent analog correlators.

Published in:

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

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