A 3.4-mW 128-MHz analog correlator for DS-CDMA wireless applications

A new analog correlator circuit for a direct sequence code division multiple access (DS-CDMA) demodulator is proposed. The circuit consists of only 13 switches, 4 capacitors and 2 level shifters. Simulation with a code length of 127 reveals that the proposed circuit dissipates 3.4 mW at 128 MHz. The proposed circuit had been implemented into a Si chip using a 0.6 /spl mu/m CMOS process. The occupation area of 256 /spl mu/m/spl times/245 /spl mu/m is estimated to be 9 times smaller compared to other reported equivalent analog correlators.