Skip to Main Content
This paper introduces a new technique that uses a differential amplifier in closed-loop negative feedback configuration to measure the offset of a dynamic latch. This offset can then be stored and canceled using standard techniques, thus allowing gain reduction in the preamplifier stages in high-resolution comparators. A CMOS comparator was designed based on the proposed technique. The output of the comparator drives a 1 pF load capacitance and is held valid for at least 75% of the cycle. The performance of the comparator was simulated using HSPICE with the worst-case combination of differences as large as 10 mV between the thresholds of nominally identical transistors, where it achieved an offset of 400 μV at a 40 MHz clock rate in 0.6 μm CMOS technology while dissipating 1 mW from a 3.3 V power supply.