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Simplified current and delay models for deep submicron CMOS digital circuits

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2 Author(s)
Mansour, M.M. ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Shanbhag, N.R.

This paper presents a model for estimating the drain current in deep submicron (DSM) CMOS devices based on Sakurai and Newton's (1991) work, and hence is referred to as the modified SN-model. The proposed model preserves the simplicity of the SN-model while providing accurate drain current estimates for varying device widths. Manually computed current and delay values for inverter circuits via the proposed model match SPICE level 49 within 1.2% average (3% maximum) error in 0.25 μm and 0.18 μm CMOS processes over a wide range of transistor widths, fanouts, and input rise/fall times. A generalized delay model for circuits with interconnect is also proposed with accuracy within 3% error over a wide range of buffer sizes and interconnect lengths. The proposed model has been successfully incorporated into a senior level circuit design course at the University of Illinois at Urbana-Champaign.

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Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on  (Volume:5 )

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