A high-speed VLSI fuzzy logic controller with pipeline architecture

We present a high-speed VLSI fuzzy logic controller, which is well suitable for real time applications. The main distinction of our approach is that it may complete the max-min calculation within one clock cycle. The speedup is achieved by an effective format for membership function and a careful analysis to the conditions of max-min calculation. As a result, the latency of a fuzzy inference can be considerably reduced. Based on the basic idea, a pipelined parallel architecture is proposed to fully utilize the parallelism inherited in the fuzzy inference. The VLSI fuzzy logic controller was implemented and simulated by using 0.35 μm cell library as the target technology. Experimental data shows that the proposed architecture achieves higher performance compared with other approaches