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Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability

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1 Author(s)
J. H. Lau ; Agilent Technol. Inc., Palo Alto, CA, USA

Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the, important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layer on the solder joint reliability of WLCSP on printed circuit board (PCB) through the creep responses such as the deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped with pad-redistribution WLCSPs are considered in this study

Published in:

IEEE Transactions on Electronics Packaging Manufacturing  (Volume:25 ,  Issue: 1 )