By Topic

Adding synchronous and LSSD modes to asynchronous circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
K. van Berkel ; Philips Res. Labs., Eindhoven, Netherlands ; A. Peeters ; F. te Beest

A synchronous mode as well as a scan mode of operation are added to a large class of asynchronous circuits, in compliance with LSSD design rules. This enables the application of mainstream tools for design-for-testability and test-pattern generation to asynchronous circuits. The approach is based on a systematic transformation of all single-output sequential gates into synchronous and scannable versions. By exploiting dynamic circuit operation in scan mode, the overhead of this transformation in terms of both circuit cost and circuit delay is kept minimal.

Published in:

Asynchronous Circuits and Systems, 2002. Proceedings. Eighth International Symposium on

Date of Conference:

8-11 April 2002