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Dual Port SRAM - Row Decoder

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1 Author(s)

Since there are 2 ports in this design, there must be 2 Row Decoders ¿ one for each port. A big portion of the challenge is to be able to lay out the both Row Decoders and have each one be able to interface with every row of bit cells. I addition to that, the inputs to from the address buffers associated with each port must be considered in how they are placed in the layout.

Persistent Link: http://ieeexplore.ieee.org/servlet/opac?mdnumber=EW1375

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Publication Date :

2014