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Derivation and implication of a novel DRAM bit cost model

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1 Author(s)
H. Nakatsuka ; Toshiba Corp., Tokyo, Japan

A model for the cost/performance of a large-scale integrated circuit (LSI) is derived using critical area with 1/x3 defect size distribution and common industry trends for device parameters and process parameters. The model predicts that dynamic random access memory bit cost will begin to increase sometime after 2005, if the current bit capacity increase rate of four times every three years remains effective. It is suggested that the rate is reduced to two times every two years, which will ensure a bit cost reduction beyond 2010. However, if the defect density can be reduced faster than the past trends, a four times bit capacity increase every three years can still remain cost effective

Published in:

IEEE Transactions on Semiconductor Manufacturing  (Volume:15 ,  Issue: 2 )