By Topic

A parallel transparent BIST method for embedded memory arrays by tolerating redundant operations

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Huang, D.C. ; Dept. of Comput. Sci. & Inf. Eng., Nat. Chung-Cheng Univ., Chiayi, Taiwan ; Jone, W.B.

In this paper, the authors propose a new transparent built-in self-test method to test in parallel multiple embedded memory arrays with various sizes. First, a new transparent test interface is designed to perform testing in the normal mode and to cope with test interrupts in a real-time manner. The circular scan test interface facilitates the processes of both test pattern generation and signature analysis. By tolerating redundant read/write/shift operations, we develop a new march algorithm called TRSMarch to achieve the goals of low hardware overhead, short test time, and high fault coverage. It can be proved that TRSMarch can detect all stuck-at faults, all transition faults, and each coupling fault occurring in different words. For each coupling fault occurring in the same word, depending on the coupling type and effect, it can be detected or its detection probability can be high as more transparent processes are executed. TRSMarch can be easily extended to deal with more faults such as single-cell read destructive faults and read destructive coupling faults

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:21 ,  Issue: 5 )