By Topic

A novel nonvolatile memory cell suitable for both flash and byte-writable applications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
J. M. Caywood ; SubMicron Circuits, San Jose, CA, USA ; Chih-Jen Huang ; Y. J. Chang

The structure, operation, and fabrication of a novel EEPROM/flash cell and array architecture are described. The cell is about half the size of the traditional floating gate tunnel oxide (FLOTOX) electrically erasable programmable read only memory (EEPROM) cell when laid out with the same design rules. This approach has a simple fabrication sequence and requires minimum overhead circuitry rendering it especially suitable for embedded applications. Characterization shows this approach has good retention and has million cycle endurance. Both read and write disturbs are characterized. There are large margins for both types of disturbs. In fact, the data on write disturbs show the disturb margins to be so large that disturb margin can be safely traded off for reduced stress on select transistors

Published in:

IEEE Transactions on Electron Devices  (Volume:49 ,  Issue: 5 )