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Design methodology of the high performance large-grain polysilicon MOSFET

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3 Author(s)
Jagar, S. ; Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, China ; Hongmei Wang ; Chan, M.

A methodology to design high-performance MOSFETs on the large-grain polysilicon-on-insulator (LPSOI) film is presented. Due to the metal-induced lateral crystallization (MILC) process in the formation of LPSOI films, the polysilicon grain locations and orientations can be reasonably controlled. Therefore, the performance of an LPSOI MOSFET can be optimized by carefully selecting the orientation and grain location according to the size of the desired transistor. The effects of various design parameters including the distance from the nickel strip, relative source/drain position, transistor orientation, and layout geometry are investigated. A ladder layout method is proposed to provide scalability in the design of high performance LPSOI MOSFETs. A design guideline for designing LPSOI NMOSFETs with different dimensions is given

Published in:

Electron Devices, IEEE Transactions on  (Volume:49 ,  Issue: 5 )

Date of Publication:

May 2002

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