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An instruction-level methodology for power estimation and optimization of embedded VLIW cores

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6 Author(s)
Bona, A. ; ALaRI, Lugano, Switzerland ; Sami, M. ; Sciuto, D. ; Silvano, C.
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Summary form only given. The overall goal of this work is to define an instruction-level power macro-modeling and characterization methodology for VLIW embedded processor cores. The approach presented in this paper is a major extension of the work previously proposed, targeting an instruction-level energy model to evaluate the energy consumption associated with a program execution on a pipelined VLIW core. Our ongoing work aims at defining a power optimization technique based on the proposed model. The technique consists of a spatial rescheduling of the operations within the same long instruction to reduce their instruction power overhead

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Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings

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